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general description the max9174/max9175 are 670mhz, low-jitter, low- skew 1:2 splitters ideal for protection switching, loop- back, and clock and signal distribution. the devices feature ultra-low 1.0ps (rms) random jitter (max) that ensures reliable operation in high-speed links that are highly sensitive to timing errors. the max9174 has a fail-safe lvds input and lvds out- puts. the max9175 has an anything differential input (cml/lvds/lvpecl) and lvds outputs. the outputs can be put into high impedance using the power-down inputs. the max9174 features a fail-safe circuit that dri- ves the outputs high when the input is open, undriven and shorted, or undriven and terminated. the max9175 has a bias circuit that forces the outputs high when the input is open. the power-down inputs are compatible with standard lvttl/lvcmos logic. the power-down inputs tolerate undershoot of -1v and overshoot of v cc + 1v. the max9174/max9175 are available in 10-pin ?ax and 10-lead thin qfn with exposed pad pack- ages, and operate from a single +3.3v supply over the -40 c to +85 c temperature range. applications protection switching loopback clock distribution features 1.0ps (rms) jitter (max) at 670mhz 80ps (p-p) jitter (max) at 800mbps data rate +3.3v supply lvds fail-safe inputs (max9174) anything input (max9175) accepts differential cml/lvds/lvpecl power-down inputs tolerate -1.0v and v cc + 1.0v low-power cmos design 10-lead ?ax and thin qfn packages -40? to +85? operating temperature range conform to ansi tia/eia-644 lvds standard iec 61000-4-2 level 4 esd rating max9174/max9175 670mhz lvds-to-lvds and anything-to-lvds 1:2 splitters ________________________________________________________________ maxim integrated products 1 ordering information clk in asic clock distribution clk in asic clk1 clk2 max9174 max9174 max9176 max9176 typical application circuit 19-2827; rev 0; 4/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max9174 eub -40 c to +85 c 10 ?ax MAX9174ETB* -40 c to +85 c 10 thin qfn-ep** max9175 eub -40 c to +85 c 10 ?ax max9175etb* -40 c to +85 c 10 thin qfn-ep** * future product?ontact factory for availability. ** ep = exposed paddle. functional diagram and pin configurations appear at end of data sheet.
max9174/max9175 670mhz lvds-to-lvds and anything-to-lvds 1:2 splitters 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ..?..-0.3v to +4.0v in+, in- to gnd..............................................-0.3v to +4.0v out_+, out_- to gnd..........................................-0.3v to +4.0v pd0 , pd1 to gnd .......................................-1.4v to (v cc + 1.4v) single-ended and differential output short-circuit duration (out_+, out_-) .....................continuous continuous power dissipation (t a = +70?) 10-pin ?ax (derate 5.6mw/? above +70?) ...........444mw 10-lead qfn (derate 24.4mw/? above +70?) ......1951mw maximum junction temperature .....................................+150? storage temperature range .............................-65? to +150? esd protection human body model (r d = 1.5k ? , c s = 100pf) in+, in-, out_+, out_-...............................................?2kv other pins (v cc , pd0 , pd1 ) ...............................................2kv iec 61000-4-2 level 4 (r d = 330 ? , c s = 150pf) contact discharge in+, in-, out_+, out_- ...................?kv air-gap discharge in+, in-, out_+, out_- .................?5kv lead temperature (soldering, 10s) .................................+300? dc electrical characteristics (v cc = +3.0v to +3.6v, r l = 100 ? ?%, pd_ = high, differential input voltage |v id | = 0.05v to 1.2v, max9174 input common-mode voltage v cm = |v id /2| to (2.4v - |v id /2|), max9175 input common-mode voltage v cm = |v id /2| to (v cc - | v id /2|), t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, |v id | = 0.2v, v cm = +1.25v, t a = +25?.) (notes 1, 2, 3) parameter symbol conditions min typ max units differential input (in+, in-) differential input high threshold v th +50 mv differential input low threshold v tl -50 mv input current i in + , i in - figure 1 -20 +20 a max9174 v cc = 0v or open, figure 1 power-off input current i in +, i in - max9175 v in + = 3.6v or 0v, v in - = 3.6v or 0v, v cc = 0v or open, figure 1 -20 +20 a r in1 60 108 fail-safe input resistors (max9174) r in2 v cc = 3.6v, 0v or open, figure 1 200 394 k ? input resistors (max9175) r in3 v cc = 3.6v, 0v or open, figure 1 212 450 k ? input capacitance c in in+ or in- to gnd (note 4) 4.5 pf lvttl/lvcmos inputs ( p p p p d d d d 0 0 0 0 , p p p p d d d d 1 1 1 1 ) input high voltage v ih 2.0 v cc + 1 v input low voltage v il -1.0 +0.8 v -1.0v pd_ 0v -1.5 ma 0v pd_ v cc -20 +20 a input current i in v cc pd_ v cc + 1.0v +1.5 ma lvds outputs (out_+, out_-) differential output voltage v od figure 2 250 393 475 mv change in differential output voltage between logic states ? v od figure 2 1.0 15 mv offset voltage v os figure 3 1.125 1.29 1.375 v
max9174/max9175 670mhz lvds-to-lvds and anything-to-lvds 1:2 splitters _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v cc = +3.0v to +3.6v, r l = 100 ? 1%, pd_ = high, differential input voltage |v id | = 0.05v to 1.2v, max9174 input common-mode voltage v cm = |v id /2| to (2.4v - |v id /2|), max9175 input common-mode voltage v cm = |v id /2| to (v cc - | v id /2|), t a = -40 c to +85 c, unless otherwise noted. typical values are at v cc = +3.3v, |v id | = 0.2v, v cm = +1.25v, t a = +25 c.) (notes 1, 2, 3) parameter symbol conditions min typ max units change in offset voltage between logic states ? v os figure 3 1.0 15 mv fail-safe differential output voltage (max9174) v od figure 2 250 393 475 mv differential output resistance r diff v cc = 3.6v or 0v 86 119 160 ? v out _+ = open, v out _- = 3.6v or 0v power-down single-ended output current i pd pd_ = low v out _- = open, v out _ + = 3.6v or 0v -1.0 0.03 +1.0 a v out _+ = open, v out _ - = 3.6v or 0v power-off single-ended output current i off pd0 , pd1 = low, v cc = 0v or open v out _- = open, v out _ + = 3.6v or 0v -1.0 0.03 +1.0 a v id = +50mv or -50mv, v out _+ = 0v or v cc output short-circuit current i os v id = +50mv or -50mv, v out _ - = 0v or v cc -15 +15 ma differential output short-circuit current magnitude ? i osd ? v id = +50mv or -50mv, v od = 0v (note 4) 15 ma pd0 = v cc , pd1 = 0v or pd0 = 0v, pd1 = v cc 17 26 supply current i cc pd0 = vcc, pd1 = vcc 25 35 ma power-down supply current i ccpd pd1 , pd0 = 0v 0.5 20 a output capacitance c o out_+ or out_- to gnd (note 4) 5.2 pf
max9174/max9175 670mhz lvds-to-lvds and anything-to-lvds 1:2 splitters 4 _______________________________________________________________________________________ ac electrical characteristics (v cc = +3.0v to +3.6v, r l = 100 ? 1%, c l = 5pf, differential input voltage |v id | = 0.15v to 1.2v, max9174 input common-mode volt- age, v cm = |v id /2| to (2.4v - |v id /2|), max9175 input common-mode voltage v cm = |v id /2| to (v cc - |v id /2|), pd_ = high, t a = -40 c to +85 c, unless otherwise noted. typical values are at v cc = +3.3v, |v id | = 0.2v, v cm = +1.25v, t a = +25 c.) (notes 5, 6, 7) parameter symbol conditions min typ max units high-to-low propagation delay t phl figures 4, 5 1.33 2.38 3.23 ns low-to-high propagation delay t plh figures 4, 5 1.33 2.39 3.23 ns added deterministic jitter t dj figures 4, 5 (note 8) 80 ps ( p-p ) added random jitter t rj figures 4, 5 1.0 ps ( rms ) pulse skew ? t plh - t phl ? t skp figures 4, 5 10 141 ps output-to-output skew t skoo figure 6 14 45 ps t skpp1 figures 4, 5 (note 9) 0.4 1.3 part-to-part skew t skpp2 figures 4, 5 (note 10) 1.9 ns rise time t r figures 4, 5 110 257 365 ps fall time t f figures 4, 5 110 252 365 ps power-down time t pd figures 7, 8 10 13 ns pd0 , pd1 = l h, figures 7, 8 18 35 s pd0 = h, pd1 = l h, figures 7, 8 92 103 power-up time t pu pd1 = h, pd0 l h, figures 7, 8 92 103 ns maximum data rate d rmax figures 4, 5, ? v od ? 250mv (note 11) 800 mbps maximum switching frequency f max figures 4, 5, ? v od ? 250mv (note 11) 670 mhz f in = 670mhz 55 65 switching supply current i ccsw f in = 155mhz 35 44 ma prbs supply current i ccpr d r = 800mbps, 2 23 - 1 prbs input 37 46 ma note 1: current into a pin is defined as positive. current out of a pin is defined as negative. all voltages are referenced to ground except v th , v tl , v id , v od , and ? v od . note 2: maximum and minimum limits over temperature are guaranteed by design and characterization. devices are 100% tested at t a = +25 c. note 3: tolerance on all external resistors (including figures) is 1%. note 4: guaranteed by design. note 5: ac parameters are guaranteed by design and characterization and are not production tested. limits are set at 6 sigma. note 6: c l includes scope probe and test jig capacitance. note 7: pulse-generator output for differential inputs in+, in- (unless otherwise noted): f = 670mhz, 50% duty cycle, r o = 50 ? , t r = 700ps, and t f = 700ps (0% to 100%). pulse-generator output for single-ended inputs pd0 , pd1 : t r = t f = 1.5ns (0.2v cc to 0.8v cc ), 50% duty cycle, v oh = v cc + 1.0v settling to v cc , v ol = -1.0v settling to zero, f = 10khz. note 8: pulse-generator output for t dj : |v od | = 0.15v, v os = 1.25v, data rate 800mbps, 2 23 - 1 prbs, r o = 50 ? , t r = 700ps, and t f = 700ps (0% to 100%). note 9: t skpp1 is the magnitude of the difference of any differential propagation delays between devices operating under identical conditions. note 10: t skpp2 is the magnitude of the difference of any differential propagation delays between devices operating over rated con- ditions. note 11: meets all ac specifications.
max9174/max9175 670mhz lvds-to-lvds and anything-to-lvds 1:2 splitters _______________________________________________________________________________________ 5 supply current vs. temperature max9174 toc01 temperature ( c) supply current (ma) 60 35 10 -15 33 34 35 36 37 38 32 -40 85 f in = 155mhz differential output voltage vs. frequency max9174 toc02 frequency (mhz) differential output voltage (mv) 700 600 400 500 200 300 100 310 320 330 340 350 360 370 380 390 400 410 300 0 800 output rise/fall time vs. temperature max9174 toc03 temperature ( c) rise/fall time (ps) 60 35 10 -15 220 230 240 250 260 270 280 290 300 210 -40 85 f in = 155mhz t r t f differential propagation delay vs. temperature max9174 toc04 temperature ( c) differential propagation delay (ns) 60 35 10 -15 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 2.0 2.1 -40 85 f in = 155mhz t phl t plh output-to-output skew vs. temperature max9174 toc05 temperature ( c) output-to-output skew (ps) 60 35 10 -15 2 4 6 8 10 12 14 16 18 20 0 -40 85 f in = 155mhz supply current vs. frequency max9174 toc06 frequency (mhz) supply current (ma) 700 600 100 200 300 400 500 25 30 35 40 45 50 55 60 20 0 800 supply current vs. data rate max9174 toc07 data rate (mbps) supply current (ma) 700 600 500 400 300 200 100 25 30 35 40 45 15 20 0 800 prbs 2 23 - 1 supply current vs. supply voltage max9174 toc08 supply voltage (v) supply current (ma) 3.5 3.4 3.3 3.2 3.1 31 32 33 34 35 36 37 38 39 40 30 3.0 3.6 f in = 155mhz output rise/fall time vs. supply voltage max9174 toc09 supply voltage (v) rise/fall time (ps) 3.5 3.4 3.3 3.2 3.1 210 220 230 240 250 260 270 280 290 300 200 3.0 3.6 f in = 155mhz t f t r typical operating characteristics ((max9174) v cc = +3.3v, |v id | = 0.15v, v cm = 1.25v, t a = +25 c, r l = 100 ? 1%, c l = 5pf, pd_ = v cc , unless otherwise noted.)
max9174/max9175 670mhz lvds-to-lvds and anything-to-lvds 1:2 splitters 6 _______________________________________________________________________________________ typical operating characteristics (continued) ((max9174) v cc = +3.3v, |v id | = 0.15v, v cm = 1.25v, t a = +25 c, r l = 100 ? 1%, c l = 5pf, pd_ = v cc , unless otherwise noted.) differential propagation delay vs. supply voltage max9174 toc10 supply voltage (v) differential propagation delay (ns) 3.5 3.4 3.3 3.2 3.1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 2.0 3.0 3.6 f in = 155mhz t plh t phl output-to-output skew vs. supply voltage max9174 toc11 supply voltage (v) output-to-output skew (ps) 3.5 3.4 3.3 3.2 3.1 1 2 3 4 5 6 7 8 9 10 0 3.0 3.6 f in = 155mhz differential output voltage vs. load resistance max9174 toc12 load resistance ( ? ) differential output voltage (mv) 140 130 120 110 100 90 80 70 60 250 300 350 400 450 500 200 50 150 propagation delay vs. input common-mode voltage max9174 toc13a input common-mode voltage (v) propagation delay (ns) 1.575 0.825 2.3 2.4 2.5 2.6 2.7 2.8 2.2 0.075 2.325 max9174 f in = 155mhz t phl t plh propagation delay vs. input common-mode voltage max9174 toc13b input common-mode voltage (v) propagation delay (ns) 2.775 2.325 1.425 1.875 0.975 0.525 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 2.0 0.075 3.225 f in = 155mhz t phl t plh output-to-output skew vs. input common-mode voltage max9174 toc14a input common-mode voltage (v) output-to-output skew (ps) 1.575 0.825 6.2 6.4 6.6 6.8 7.0 7.2 7.4 7.6 7.8 8.0 6.0 0.075 2.325 max9174 f in = 155mhz output-to-output skew vs. input common-mode voltage max9174 toc14b input common-mode voltage (v) output-to-output skew (ps) 2.775 2.325 0.525 0.975 1.425 1.875 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 0.075 3.225 max9175 f in = 155mhz
detailed description the max9174/max9175 are 670mhz, low-jitter, low- skew 1:2 splitters ideal for protection switching, loop- back, and clock and signal distribution. the devices feature ultra-low 80ps p-p deterministic jitter (max) that ensures reliable operation in high-speed links that are highly sensitive to timing error. the max9174 has a fail-safe lvds input and lvds out- puts. the max9175 has an anything differential input (cml/lvds/lvpecl) and lvds outputs. the outputs can be put into high impedance using the power-down inputs. the max9174 features a fail-safe circuit that dri- ves the outputs high when the input is open, undriven and shorted, or undriven and terminated. the max9175 has a bias circuit that forces the outputs high when the input is open. the power-down inputs are compatible with standard lvttl/lvcmos logic. the power-down inputs tolerate undershoot of -1v and overshoot of vcc + 1v. the max9174/max9175 are available in 10-pin max and 10-lead thin qfn pack- ages, and operate from a single +3.3v supply over the -40 c to +85 c temperature range. current-mode lvds outputs the lvds outputs use a current-steering configuration. this approach results in less ground bounce and less output ringing, enhancing noise margin and system speed performance. a differential output voltage is produced by steering current through the parallel combination of the integrat- ed differential output resistor and transmission line impedance/termination resistor. when driving a 100 ? termination resistor, a differential voltage of 250mv to 475mv is produced. for loads greater than 100 ? , the output voltage is larger, and for loads less than 100 ? , the output voltage is smaller. see the differential output voltage vs. load resistance curve in typical operating characteristics for more information. the outputs are short-circuit current limited for single-ended and differ- ential shorts. max9174 input fail-safe the fail-safe feature of the max9174 sets the outputs high when the differential input is: open undriven and shorted undriven and terminated without a fail-safe circuit, when the input is undriven, noise at the input may switch the outputs and it may appear to the system that data is being sent. open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when a driver output is in high impedance. a shorted input can occur because of a cable failure. max9174/max9175 670mhz lvds-to-lvds and anything-to-lvds 1:2 splitters _______________________________________________________________________________________ 7 pin description pin max qfn name function 1 1 in+ noninverting differential input 2 2 in- inverting differential input 3 3 gnd ground 44 pd0 lvttl/lvcmos input. out0+, out0- are high impedance to ground when pd0 is low. internal pulldown resistor to gnd. 55 pd1 lvttl/lvcmos input. out1+, out1- are high impedance to ground when pd1 is low. internal pulldown resistor to gnd. 6 6 out0- inverting lvds output 0 7 7 out0+ noninverting lvds output 0 88v cc power supply 9 9 out1- inverting lvds output 1 10 10 out1+ noninverting lvds output 1 ep exposed pad exposed pad. solder to ground.
max9174/max9175 when the input is driven with a differential signal of |v id | = 50mv to 1.2v within a voltage range of 0 to 2.4v, the fail-safe circuit is not activated. if the input is open, undriven and shorted, or undriven and terminated, an internal resistor in the fail-safe circuit pulls the input above vcc - 0.3v, activating the fail-safe circuit and forcing the outputs high (figure 1). overshoot and undershoot voltage protection the max9174/max9175 are designed to protect the power-down inputs ( pd0 and pd1 ) against latchup due to transient overshoot and undershoot voltage. if the input voltage goes above vcc or below gnd by up to 1v, an internal circuit limits input current to 1.5ma. applications information power-supply bypassing bypass the v cc pin with high-frequency surface-mount ceramic 0.1f and 0.001f capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to v cc . differential traces input and output trace characteristics affect the perfor- mance of the max9174/max9175. use controlled- impedance differential traces (100 ? typ). to reduce radiated noise and ensure that noise couples as com- mon mode, route the differential input and output sig- nals within a pair close together. reduce skew by matching the electrical length of the two signal paths that make up the differential pair. excessive skew can result in a degradation of magnetic field cancellation. maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. minimize the number of vias to further prevent imped- ance discontinuities. cables and connectors interconnect for lvds typically has a controlled differ- ential impedance of 100 ? . use cables and connectors that have matched differential impedance to minimize impedance discontinuities. avoid the use of unbalanced cables such as ribbon or simple coaxial cable. balanced cables such as twisted pair offer superior signal quality and tend to generate less emi due to magnetic field canceling effects. balanced cables pick up noise as common mode, which is rejected by the lvds receiver. termination the max9174/max9175 require external input and out- put termination resistors. for lvds, connect an input termination resistor across the differential input and at the far end of the interconnect driven by the lvds out- puts. place the input termination resistor as close to the receiver input as possible. termination resistors should match the differential impedance of the transmission line. use 1% surface-mount resistors. 670mhz lvds-to-lvds and anything-to-lvds 1:2 splitters 8 _______________________________________________________________________________________ input outputs (in+) - (in-) (out_+) - (out_-) +50mv h -50mv l -50mv < vid < +50mv indeterminate max9175 open max9174 open, undriven short, or undriven parallel termination h table 1. input function table p p p p d d d d 1 1 1 1 p p p p d d d d 0 0 0 0 out_+, out_- h h both outputs enabled l or open l or open shutdown to minimum power, outputs high impedance to ground l or open high out0 enabled, out1 high impedance to ground high l or open out1 enabled, out0 high impedance to ground table 2. power-down function table in+ to output in- in+ in- max9175 input max9174 internal fail-safe circuit differential rcvr comparator r in3 r in3 v cc - 0.3v v cc r in2 r in1 r in1 v cc figure 1. input structure
the max9174/max9175 feature an integrated differen- tial output resistor. this resistor reduces jitter by damp- ing reflections produced by a mismatch between the transmission line and termination resistor at the far end of the interconnect. board layout separate the differential and single-ended signals to reduce crosstalk. a four-layer printed circuit board with separate layers for power, ground, differential signals, and single-ended logic signals is recommended. separate the differential signals from the logic signals with power and ground planes for best results. iec 61000-4-2 level 4 esd protection the iec 61000-4-2 standard (figure 9) specifies esd tolerance for electronic systems. the iec 61000-4-2 model specifies a 150pf capacitor that is discharged into the device through a 330 ? resistor. the max9174/ max9175 differential inputs and outputs are rated for iec 61000-4-2 level 4 (8kv contact discharge and 15kv air-gap discharge). the human body model (hbm, figure 10) specifies a 100pf capacitor that is discharged into the device through a 1.5k ? resistor. iec 61000-4-2 level 4 discharges higher peak current and more energy than the hbm due to the lower series resistance and larger capacitor. max9174/max9175 670mhz lvds-to-lvds and anything-to-lvds 1:2 splitters _______________________________________________________________________________________ 9 v test = 0 to v cc v od in+ 5k ? 5k ? 1.25v 1.20v 1.25v 1.20v in- r l out_ - out_+ figure 2. v od test circuit in+ 1.25v 1.20v 1.25v 1.20v in- r l /2 r l /2 out_ - vos out_+ figure 3. v os test circuit pulse generator 50 ? c l 50 ? c l v test = 0 to v cc in+ 5k ? 5k ? in- r l out0- out0+ c l c l 5k ? 5k ? r l out1- out1+ figure 4. transition time, propagation delay, and output-to-output skew test circuit
max9174/max9175 670mhz lvds-to-lvds and anything-to-lvds 1:2 splitters 10 ______________________________________________________________________________________ in+ in- out0+ out0- out1+ out1- t skoo t skoo figure 6. output-to-output skew t phl t plh 80% 20% 20% 80% 0v v od- v od+ 0v v os = ((v out_ +) + (v out_- ))/2 in- in+ out_- (out_+) - (out_-) out_+ t f t r figure 5. transition time and propagation delay timing
max9174/max9175 670mhz lvds-to-lvds and anything-to-lvds 1:2 splitters ______________________________________________________________________________________ 11 50% pd_ 50% 50% 1.25v 1.25v 50% out_+ when v id = +50mv out_- when v id = -50mv out_+ when v id = -50mv out_- when v id = +50mv t pu t pu t pd t pd v cc + 1v v cc v oh v ol v cc /2 0 -1.0v figure 7. power-up/down delay waveform out1+ out1- out0+ out0- in+ in- max9174 max9175 1.25v 1.20v 1.25v 1.20v r l /2 r l /2 1.25v r l /2 r l /2 1.25v pulse generator 50 ? figure 8. power-up/down delay test circuit
max9174/max9175 670mhz lvds-to-lvds and anything-to-lvds 1:2 splitters 12 ______________________________________________________________________________________ charge-current- limit resistor discharge resistance storage capacitor c s 150pf r c 50 ? to 100 ? r d 330 ? high- voltage dc source device under test figure 9. iec 61000-4-2 contact discharge esd test model charge-current- limit resistor discharge resistance storage capacitor c s 100pf r c 1m ? r d 1.5k ? high- voltage dc source device under test figure 10. human body esd test model lvds driver 0 lvds driver 1 out1+ out1- out0+ out0- in+ in- pd0 pd1 max9174 max9175 differential receiver functional diagram 1 2 3 4 5 10 9 8 7 6 out1+ out1- v cc out0+ pd0 gnd in- in+ max9174 max9175 max top view out0- exposed pad 10 9 8 7 6 out1+ out1- v cc out0+ out0- pd1 1 2 3 4 5 pd0 gnd in- in+ pd1 max9174 max9175 thin qfn (leads under package) pin configurations chip information transistor count: 693 process: cmos
max9174/max9175 670mhz lvds-to-lvds and anything-to-lvds 1:2 splitters ______________________________________________________________________________________ 13 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) 10lumax.eps package outline, 10l umax/usop 1 1 21-0061 i rev. document control no. approval proprietary information title: top view front view 1 0.498 ref 0.0196 ref s 6 side view bottom view 0 0 6 0.037 ref 0.0078 max 0.006 0.043 0.118 0.120 0.199 0.0275 0.118 0.0106 0.120 0.0197 bsc inches 1 10 l1 0.0035 0.007 e c b 0.187 0.0157 0.114 h l e2 dim 0.116 0.114 0.116 0.002 d2 e1 a1 d1 min -a 0.940 ref 0.500 bsc 0.090 0.177 4.75 2.89 0.40 0.200 0.270 5.05 0.70 3.00 millimeters 0.05 2.89 2.95 2.95 - min 3.00 3.05 0.15 3.05 max 1.10 10 0.60.1 0.60.1 ?0.500.1 h 4x s e d2 d1 b a2 a e2 e1 l l1 c gage plane a2 0.030 0.037 0.75 0.95 a1
max9174/max9175 670mhz lvds-to-lvds and anything-to-lvds 1:2 splitters maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) 6, 8, &10l, qfn thin.eps proprietary information title: approval document control no. rev. 2 1 package outline, 6, 8 & 10l, tdfn, exposed pad, 3x3x0.80 mm 21-0137 d l c l c semiconductor dallas a2 a pin 1 index area d e a1 d2 b e2 [(n/2)-1] x e ref. e k 1n 1 l e l a l pin 1 id c0.35 detail a e number of leads shown are for reference only document control no. approval title: proprietary information rev. 2 2 common dimensions symbol min. max. a 0.70 0.80 d 2.90 3.10 e 2.90 3.10 a1 0.00 0.05 l 0.20 0.40 pkg. code 6 n t633-1 1.500.10 d2 2.300.10 e2 0.95 bsc e mo229 / weea jedec spec 0.400.05 b 1.90 ref [(n/2)-1] x e 1.500.10 mo229 / weec 1.95 ref 0.300.05 0.65 bsc 2.300.10 t833-1 8 package variations 21-0137 0.250.05 2.00 ref mo229 / weed-3 0.50 bsc 1.500.10 2.300.10 10 t1033-1 0.25 min. k a2 0.20 ref. d semiconductor dallas package outline, 6, 8 & 10l, tdfn, exposed pad, 3x3x0.80 mm

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